A so-called cyclic type using a memory is known as a noise reducing circuit for reducing noises of digital signals, and particularly it is broadly applied in a case where noise reduction is carried out on digital video signals.
The applicant of this application previously proposed the construction of such a noise reducing circuit, and FIG. 11 shows the noise reducing circuit constructed on the basis of the previous proposal.
In the noise reducing circuit shown in FIG. 11, a video signal as a digital signal is first input to an input terminal 1. The video signal is a video signal based on the Interlace system in which even fields and odd fields are interlaced with one another, represented by the NTSC system, the PAL system or the like, for example.
An input video signal Din input to the input terminal 1 as described above is branched and input to an interpolating filter 2 and a subtracter 9, respectively.
The subtracter 9 subtracts a signal processed in a non-linear processing circuit 8 described later from the input video signal Din and outputs the subtraction result to an output terminal 13. As a result, a video signal output from which noises are reduced is achieved at the output terminal 13.
The video signal output supplied from the subtracter 9 to the output terminal 13 is branched and output to a field memory 4, and written in the field memory 4.
The output from the field memory 4 corresponds to a preceding field video signal Dpre which is preceding to the current field by one field. The preceding field video signal Dpre is output to an interpolating filter 5.
Here, the video signal of the current field (field image data) is input to the interpolating filter 2 to which the input video signal Din is input, and the preceding field video signal Dpre which is delayed at the timing corresponding to one field by the field memory 4 is input to the interpolating filter 5.
The interpolating filters 2, 5 will be later described in detail in the following embodiments, however, the interpolation of pixels in the vertical direction of input video signals is carried out in these filters by setting required coefficients for the pixels in the vertical direction. The setting of the coefficients in the interpolating filters 2, 5 is alternately switched at the timing corresponding to each field period in accordance with the phase relationship between the current field image and the field image which is preceding to the current field image by one field.
The spatial phase relationship of the pixels in the vertical direction is made coincident between interpolation video signals Dp1, Dp2 output from the interpolating filters 2 and 5 by performing the interpolation processing in each of the interpolating filters 2, 5.
The interpolation video signals Dp1, Dp2 which have been subjected to the interpolation processing in the interpolating filters 2, 5 are written in work memories 3, 6 respectively.
Each of the work memories 3, 6 comprises a delay circuit such as a delay line or the like.
In this case, a video signal is supplied from each of the work memories 3, 6 to a motion vector detection circuit 10.
The interpolation video signal Dp1 of the current field timing is output from the work memory 3, however, the interpolation video signal Dp2 which is delayed by one field with respect to the current field is output from the work memory 6.
In the motion vector detection circuit 10, a motion vector is detected by using the video signals which are input from the work memories 3 and 6 and have the time difference corresponding to one field.
Furthermore, a vector validity/invalidity judging circuit 11 judges validity/invalidity of a candidate vector detected in the motion vector detection circuit 10. That is, it is judged whether the candidate vector is applied to motion compensation or not.
A memory controller 12 controls the work memories 3, 6 with respect to the motion compensation on the basis of the judgment result of the vector validity/invalidity judging circuit 11. That is, if it is judged in the vector validity/invalidity judging circuit 11 that the candidate vector is valid, the memory controller 12 transmits motion compensation control signals to the work memories 3, 6 so that the motion compensation processing is carried out on the video signals on the basis of the candidate vector.
Furthermore, under the control of the memory controller 12, video signals are read out from the work memories 3, 6 so that the motion compensation is carried out by using a detected motion vector. The video signals thus read out are supplied to the subtracter 7 to calculate the subtraction between the video signals, whereby a motion-compensated signal is attained as a differential signal achieved by subtracting the video signal output from the work memory 6 from the video signal output from the work memory 3.
The non-linear processing circuit 8 carries out attenuation processing on the differential signal output from the subtracter 7 by using a required characteristic curve. That is, small-amplitude signal components are extracted from the differential signal output from the subtracter 7, so that noise component signals comprising noise components are extracted. The output of the non-linear processing circuit 8 is input to the subtracter 9.
In the subtracter 9, the output signal of the non-linear processing circuit 8 which corresponds to the noise component signals is subtracted from the input video signal Din.
The signal achieved through the subtraction described above in the subtracter 9 is output as a noise-reduced video signal from the output terminal 13. Further, the signal is also written in the field memory 4 and used for the noise reducing processing at the next field timing.
In the case of VTR (Video Tape Recorder) or the like, not only normal equi-speed reproduction is carried out, but also speed-varied reproduction such as fast feeding, rewinding, picture search, etc. is carried out.
Here, when a video signal is based on the interlace system, with respect to a video signal reproduced on the basis of the normal equal-speed reproduction, the horizontal synchronous pulses of the video signals of even fields and odd fields are shifted from each other in phase position by 0.5 line with respect to the vertical synchronous pulses. In this case, such a signal will be referred to as “standard signal”.
On the other hand, with respect to a video signal reproduced on the basis of the speed-varied reproduction, the horizontal synchronous pulses of the video signal of the even fields and the odd fields are in phase with respect to the vertical synchronous pulses. In this case, such a signal will be referred to as “non-standard signal”.
Therefore, considering a case where the noise reducing circuit shown in FIG. 11 is installed in a device like VTR in which not only a standard signal is reproduced, but also a non-standard signal based on the speed-varied reproduction or the like may be reproduced, the noises can be normally reduced by the operation described with reference to FIG. 11 when the standard signal is input.
However, when the non-standard signal is input, the horizontal synchronous pulses of the video signals of the even fields and the odd fields are in phase, so that it cannot be correctly judged whether the current field is an even field or an odd field. If the noise reducing operation containing the interpolation processing by the interpolating filters 2, 5 is carried out under the above state, the noises could not be effectively reduced.
As an example of the improper noise reducing operation, as the principle will be described later, there is such a case that a noise to be reduced is viewed as moving to the upper side or lower side on an image. It has been found that when the noise reduction processing is normally carried out on the standard signal, the noise is reduced at the same position, however, when the noise to be reduced moves as described above, it is more conspicuous than when the noise is reduced at the same position, and thus pictures are more seamy.
As described above, the construction of the present noise reducing device has the problem that the noise reducing performance at the input time of the non-standard signal is not sufficiently high.